-----------------------------------------------------------
--Archivo: element.vhd 			                 --
--Fecha de creación: 20/01/2011				 --
--Última fecha de modificación: 24/01/2011		 --
--Diseñador: Typson Sanchez				 --
--Diseño: Elemento de Memoria.				 --
--Propósito: Elemento de 4bits para el almacenamiento 	 --
--en la memoria				 		 --
-----------------------------------------------------------
entity element is
  port(
    DATAIN        : in std_logic_vector(3 downto 0);
    ELEMENT_ENABLE  : in  std_logic;
    WRITE_ENABLE : in  std_logic;
    CLK          : in  std_logic;
    DATAOUT       : out std_logic_vector(3 downto 0)
  );
end element;

architecture structural of element is
   
  component cell
    port(
      INPUT        : in  std_logic;
      CELL_ENABLE  : in  std_logic;
      WRITE_ENABLE : in  std_logic;
      CLK          : in  std_logic;
      OUTPUT       : out std_logic
    );
  end component;

begin

  cell_gen : for i in 0 to 3 generate
   cell_row: cell port map(
     INPUT         => DATAIN(i),
     CELL_ENABLE   => ELEMENT_ENABLE,
     WRITE_ENABLE  => WRITE_ENABLE,
     CLK           => CLK,
     OUTPUT        => DATAOUT(i)
   );
  end generate;

end structural;
